Stefan Wallentowitz

We have a massive amount of wiring and only in some parts we have before replaced parts of it with interfaces. Those have been a pain before, but we should...

System 3x3 PGAS

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This is a 3x3 system with the memory tile in the center of the system: ``` CT CT CT CT MT CT CT CT CT ``` Beside Verilator simulation it...

PGAS system

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Merge the PGAS (Partitioned Global Address Space) work from before into the current compute tile, so that `compute_tile_dm` and `compute_tile_pgas` become one `compute_tile`. The global configuration parameter is then `MEMORY_ACCESS`...

Register ecall hook from Driver

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Unified JS interface to sim via Driver to register ecall hooks. Requires this to be merged into the backend: https://github.com/ThaumicMekanism/venusbackend/pull/7

[WIP] Draft FX3 firmware interface

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It not make sense to load our firmware to the ZTEX boards, because we would loose the ability to load the FPGA bitstream. Also we don't want to include this...

FX3: 32 bit protocol

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To gain more bandwidth we can use another signaling protocol on the FX3 (and other 32 bit wide physical interfaces). ## Problem GLIP is inteded to provide a 16 bit...

Auto-detect UART

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We should start the UART transfers with a training sequence and auto-detect the baud speed with it.

We currently need RTS/CTS to handle flow control between the chip and the FPGA. We can add XON/XOFF, but need extra care for those characters then. Potentially we can then...