RISC-V backend

[BananaEarwig]

Hi again, For another side project I'm going to be working on implementing a RISC-V compliant CPU and I thought as an additional test an for general fun and games, getting ChrysaLisp running on it would be a very interesting experiment.

So, …. where should I start looking in order to add another backend.

Thanks, Martyn

[vygr]

First place to start would be the looking at the sys/arm.inc file. Copy that to a sys/riscv.inc and use it as a template for the RISC V.

Another question is we need 64bit RISC V unless there will be a lot of issues to address ! Was your fpga going to be 64bit ?

Create a riscv branch too for this to go in while it being worked on.

Would you be planning on having Linux or such on the fpga ? Or bare metal with ChrysaLisp direct on top ?

Chris

[TheMartynBliss]

The original plan was for 32bit but eventually 64 bit was planned so its just a slight reordering. Initially bare metal as I dont want to add the other things that a linux kernel needs from the getgo.

[vygr]

Yeah, 32bit does bring a lot of issue we can skip by having 64bit registers.

So eventually we will have to face the prospect of doing something with the main.c host interface for your FPGA. I'd say we first of all just go for getting the TUI stuff working after your happy with the RISC V backends code output.

[vygr]

Happy to say this is now done. :)