Vrtgs

Make Vec3A implement NoUninit or Possibly Pod

1

Implement [NoUnint](https://docs.rs/bytemuck/latest/bytemuck/trait.NoUninit.html) and possibly Pod on Vec3A since sometimes its useful to have a byte view of the array for example, vec3 in wgsl has an align of 16 so...

The full tokio port, Sadly there is no change in performance detected.

4

That being said this was only benchmarked on my local windows machine with only a handful of ports open, not the whole internet

add f16 and f128 support

2

add initial support for f16 and f128, next steps are to add this support in serde_test if this lands helps with adding ecosystem support par in rust-lang/rust#116909

suspicious discarding of buffer

1

code for encoding [here](https://github.com/xiph/rav1e/blob/b7bf39066ec4f004c9b9cdb81c91734ec2edfac7/src/encoder.rs#L3785-L3793) creates a new buffer called t35_buf then writes it... then clears it before it gets dropped? https://github.com/xiph/rav1e/blob/b7bf39066ec4f004c9b9cdb81c91734ec2edfac7/src/encoder.rs#L3785-L3793 there is also the fact that this suspicously isn't...