Murali Vijayaraghavan

I created a smaller example showcasing bufferization issue: `iree-opt --pass-pipeline='iree-codegen-iree-comprehensive-bufferize' --split-input-file test.mlir` ``` func.func @test() { %cst = arith.constant dense : vector %c0 = arith.constant 0 : index %c0_i32 =...

Okay, so what is the procedure to provide feedback or request for changes to this spec?

I agree this specific extension proposal is orthogonal to the current version of the spec. Perhaps this issue can be closed and I can join the slack channel.

With traditional virtual memory, one cannot guarantee non-aliasing into shared libraries/resources (unless you are talking about a single-address space, but that voids the memory protection given by separate virtual address...

> You missed: > 4. Virtualise the address space so you don't have to deal with holes, high addresses, etc and can instead choose the exact layout of your address...

(6) Page sharing is not something we would need to support in a single-address space virtual memory.

> Those need a PA in your PTE, at which point who cares about a few extra permissions. Yes, I need a PA in my PTE. I am not trying...

> Introducing a "hardware trusts software to not create virtual page aliases, else nasal demons" rule seems at odds with CHERI's design principles of hardware-assisted checking and minimizing the trusted...

Thanks @jonwoodruff I will get around to posting there.

I understood the first part of your suggestion which basically clears the tag bit on illegal writes instead of legalizing and then clearing the tag bits if representability check fails....