Vladimir

Try a shallower model and also try to get rid of the `same` padding as this results in padding layer being inserted. It will simplify the design and hopefully speed...

Not sure, but the deeper the model is, the more tasks need to be scheduled in the dataflow region, so it becomes harder for the compiler to organize the fifo...

The separate IP was tried before in Aigean ([code](https://github.com/tarafdar/AIgean), [paper](https://dl.acm.org/doi/abs/10.1145/3482854)) but this is based on a now old version of hls4ml, when we didn't have support for QKeras. I played...

Thanks Jonathan. Can you add the before and after synthesis results to demonstrate the change?

hls4ml (currently) stores all weights on-chip in order to minimize the latency of the designs. Naturally, this is limiting the size of the models and as you have observed it...

This has been broken for some time now, I observed it as well while playing with Vitis. Thanks for looking into it.

@Jonathan-Shoemaker since #600 has been merged, can you rebase?

I need some more time to go through this.

This is probably due to changes in the h5py. What version are you using?

There's a notebook log that should say the reason for the compilation failure, can you share that as well?