[Hardware][Intel] Add CPU inference backend

[bigPYJ1151]

This PR adds a new CPU backend to vLLM and supports the basic model inference feature, with BF16 and FP32 dtype. FP16 support and TP support will be added in the future.

Changes to vLLM:

• Added VLLM_TARGET_DEVICE ENV to specify backend explicitily.
• Added CPUExecutor to isolate CPU backend with others.
• Added TorchSDPABackend to support MHA on CPU.
• Added _C related kernels on CPU.
• Forwarded DeviceConfig to CacheEngine to avoid cuda hardcoded device memory allocation.
• Added documents with install instructions.

RFC: #3654

---

PR Checklist (Click to Expand)

Thank you for your contribution to vLLM! Before submitting the pull request, please ensure the PR meets the following criteria. This helps vLLM maintain the code quality and improve the efficiency of the review process.

PR Title and Classification

Only specific types of PRs will be reviewed. The PR title is prefixed appropriately to indicate the type of change. Please use one of the following:

• [Bugfix] for bug fixes.
• [CI/Build] for build or continuous integration improvements.
• [Doc] for documentation fixes and improvements.
• [Model] for adding a new model or improving an existing model. Model name should appear in the title.
• [Frontend] For changes on the vLLM frontend (e.g., OpenAI API server, LLM class, etc.)
• [Kernel] for changes affecting CUDA kernels or other compute kernels.
• [Core] for changes in the core vLLM logic (e.g., LLMEngine, AsyncLLMEngine, Scheduler, etc.)
• [Hardware][Vendor] for hardware-specific changes. Vendor name should appear in the prefix (e.g., [Hardware][AMD]).
• [Misc] for PRs that do not fit the above categories. Please use this sparingly.

Note: If the PR spans more than one category, please include all relevant prefixes.

Code Quality

The PR need to meet the following code quality standards:

• We adhere to Google Python style guide and Google C++ style guide.
• Pass all linter checks. Please use format.sh to format your code.
• The code need to be well-documented to ensure future contributors can easily understand the code.
• Include sufficient tests to ensure the project to stay correct and robust. This includes both unit tests and integration tests.
• Please add documentation to docs/source/ if the PR modifies the user-facing behaviors of vLLM. It helps vLLM user understand and utilize the new features or changes.

Notes for Large Changes

Please keep the changes as concise as possible. For major architectural changes (>500 LOC excluding kernel/data/config/test), we would expect a GitHub issue (RFC) discussing the technical design and justification. Otherwise, we will tag it with rfc-required and might not go through the PR.

What to Expect for the Reviews

The goal of the vLLM team is to be a transparent reviewing machine. We would like to make the review process transparent and efficient and make sure no contributor feel confused or frustrated. However, the vLLM team is small, so we need to prioritize some PRs over others. Here is what you can expect from the review process:

• After the PR is submitted, the PR will be assigned to a reviewer. Every reviewer will pick up the PRs based on their expertise and availability.
• After the PR is assigned, the reviewer will provide status update every 2-3 days. If the PR is not reviewed within 7 days, please feel free to ping the reviewer or the vLLM team.
• After the review, the reviewer will put an action-required label on the PR if there are changes required. The contributor should address the comments and ping the reviewer to re-review the PR.
• Please respond to all comments within a reasonable time frame. If a comment isn't clear or you disagree with a suggestion, feel free to ask for clarification or discuss the suggestion.

Thank You

Finally, thank you for taking the time to read these guidelines and for your interest in contributing to vLLM. Your contributions make vLLM a great tool for everyone!

[WoosukKwon]

Hi @bigPYJ1151 Thanks for updating the PR! It looks really nice.

Just for other people's understanding, could you write an RFC about the overall design, supported features, key technical decisions, and integration plan? I think this should be easy since you already wrote most of them in the previous PR. Please check out #3620 and #1866 for reference.

[bigPYJ1151]

@WoosukKwon Sure, please refer to #3654

[hustnn]

Is there initial performance result for cpu reference?

[zhouyuan]

Hi @hustnn ,

In general the performance number on CPU is not as good as GPU, for both latency and throughput. However we do find there are two value proposition for vLLM w/ CPU based on our initial tests:

• much higher throughput vs naïve/static batching solutions(TGI), this is due to the great throughput oriented design of vLLM
• for near-offline inference cases, vLLM w/ CPU throughput performance is competitive vs. entry-level GPU, mostly due to the much larger KV cache space(vs. GPU). The cost for CPU based solution may also be lower.

thanks, -yuan

[hustnn]

In general the performance number on CPU is not as good as GPU, for both latency and throughput. However we do find there are two value proposition for vLLM w/ CPU based on our initial tests:

• much higher throughput vs naïve/static batching solutions(TGI), this is due to the great throughput oriented design of vLLM
• for near-offline inference cases, vLLM w/ CPU throughput performance is competitive vs. entry-level GPU, mostly due to the much larger KV cache space(vs. GPU). The cost for CPU based solution may also be lower.

@zhouyuan Thanks for your reply, it is very helpful. These 2 points match our requirement quite well. We are planning to integrate a inference operator into a olap database, we care more about throughput compared to latency since we are targeting some offline analysis scenario.

Do you have any suggestion on how should we start with some experiment? Should we wait for these MR to be merged? We want to get some initial number on the throughput and see it is acceptable or any improvement we can further do from DB's aspect.

I also found a article from intel, is it the result and method consistent with your testing? https://medium.com/@NeuralCompressor/llm-performance-of-intel-extension-for-transformers-f7d061556176

[zhouyuan]

In general the performance number on CPU is not as good as GPU, for both latency and throughput. However we do find there are two value proposition for vLLM w/ CPU based on our initial tests:

• much higher throughput vs naïve/static batching solutions(TGI), this is due to the great throughput oriented design of vLLM
• for near-offline inference cases, vLLM w/ CPU throughput performance is competitive vs. entry-level GPU, mostly due to the much larger KV cache space(vs. GPU). The cost for CPU based solution may also be lower.

@zhouyuan Thanks for your reply, it is very helpful. These 2 points match our requirement quite well. We are planning to integrate a inference operator into a olap database, we care more about throughput compared to latency since we are targeting some offline analysis scenario.

Do you have any suggestion on how should we start with some experiment? Should we wait for these MR to be merged? We want to get some initial number on the throughput and see it is acceptable or any improvement we can further do from DB's aspect.

Hi @hustnn The dockerfile in this patch maybe a good start to check: https://github.com/vllm-project/vllm/blob/384623538c081ed621b04c1eec107132920e5045/Dockerfile.cpu

If build successfully, the docker image should be enough to run some benchmarks via the scripts provided in vLLM: https://github.com/vllm-project/vllm/tree/main/benchmarks

Please note you may need to set some params to do NUMA binding as this may impact the performance for vLLM w/ CPU

For real deployment, vLLM provides the several methods to expose the service endpoint: https://docs.vllm.ai/en/latest/serving/deploying_with_docker.html You may then connect your application to the vLLM endpoint via langchain or other soltuons.

I also found a article from intel, is it the result and method consistent with your testing? https://medium.com/@NeuralCompressor/llm-performance-of-intel-extension-for-transformers-f7d061556176

Yes, the performance is improved if using INT4 quantization from Intel extension for transformers. Intel PyTorch extensions is also a good refence. Here's the link to the project: https://intel.github.io/intel-extension-for-pytorch/cpu/latest/tutorials/performance.html

thanks, -yuan

[WoosukKwon]

@bigPYJ1151 @zhouyuan QQ: Can we use torch.compile to auto-generate the custom C++ kernels except PagedAttention? This would increase the maintainability of the code a lot. I'm wondering how torch.compile performs on Intel CPUs.

[bigPYJ1151]

@WoosukKwon Agree, I think this might be a good direction to try. For these element-wise operations and normalization operations, using torch.compile would unify the front-end to Python code and use different device backends to apply optimizations and generate binary code.

TorchInductor has two IR lowering path:

• PyTorch → TorchDynamo → TorchInductor → Triton → NVIDIA GPU
• PyTorch → TorchDynamo → TorchInductor → OpenMP (C++) → CPU

The second path is designed for CPU, and is under active development and evolution. Here is a blog contains some examples for your reference.

We need to further check the current development status and any gaps to utilize it to vLLM.

[bigPYJ1151]

@WoosukKwon Thanks for your comments! I have fixed most of them. For CPUModelRunner, yes, you are right, isolate it with ModelRunner will avoid potential code breaks completely. We can do it in the future to reduce the PR size.

[bigPYJ1151]

Hi @WoosukKwon Thanks for your further comments. I have fixed them all, please check, thanks.

[bigPYJ1151]

Hi @WoosukKwon Thanks for your efforts to review this large PR!

I have added a CI script for the CPU, with building and offline inference. It was deployed on vLLM build instance and worked well. What do you think about it?

[hustnn]

hi @zhouyuan @bigPYJ1151 , Thanks for your great work! Do you have plan to public some results on cpu inference with vllm?

[zhouyuan]

@bigPYJ1151 @zhouyuan @jikunshang LGTM! Huge thanks for the great work! Very excited to finally have the CPU backend.

Please continue to work on investigating torch.compile and separating out ModelRunner for CPUs. These will increase the maintainability of the backend. Thanks again for the great work!

@WoosukKwon thanks for the detailed review and much appreciated on your guidance! Sure, will follow up on the refactoring, features and performance optimizations.

thanks, -yuan

[zhouyuan]

hi @zhouyuan @bigPYJ1151 , Thanks for your great work! Do you have plan to public some results on cpu inference with vllm?

Hi @hustnn,

We are now reviewing/seeking approval for the performance data, should be able to publish the perf data soon if everything goes well.

thanks, -yuan

[hustnn]

hi @zhouyuan @bigPYJ1151 , Thanks for your great work! Do you have plan to public some results on cpu inference with vllm?

Hi @hustnn,

We are now reviewing/seeking approval for the performance data, should be able to publish the perf data soon if everything goes well.

thanks, -yuan

@zhouyuan Thanks and look forward to the performance report.

[abhilash1910]

Great work @bigPYJ1151 @zhouyuan @jikunshang ! Looking forward to #3814 . Thanks @WoosukKwon for awesome collaboration!.

[markluofd]

Will intel cpu backend be equipped with AsyncLLMEngine? api_server is currently using AsyncLLMEngine

[bigPYJ1151]

Hi @markluofd the online inference of the CPU backend is still under tunning, we will enable it when it is ready.

[markluofd]

@bigPYJ1151 To imitate the code of https://github.com/vllm-project/vllm/pull/3814/files#diff-d1c5ec4ddd588e3b7cac13bde85a98ac5b20686dc16b9da3b1c324467c3be2b5 url, I added CPUExecutorAsync in cpu_executor.py. AsyncLLMEngine and api_server can work normally. I want to know if this method will affect the inference performance of the CPU.

[bigPYJ1151]

@markluofd Yes, the performance may have some regression. Because the CPU inference thread pool(OpenMP), HTTP service thread pool, and tokenizer threads will scramble CPU cores. We plan to isolate the inference thread pool from others to avoid this problem.

[markluofd]

@bigPYJ1151 ok, thanks！There is another question , the introduction says that only bf16 and fp32 are supported. I found that if the dtype is fp16, the CPU backend can also execute normally. I want to know whether it uses the fp16 or fp32 kernel ？(My machine is a 3rd generation cpu with no avx512_bf16 instruction)

[bigPYJ1151]

@markluofd FP16 will be cast to BF16 right now. BF16 is always supported even if there is no avx512_bf16 ISA. Pure FP16 support will be added soon, might be at the end of the month.

[markluofd]

@bigPYJ1151 I get it, thank you! I need to find a 4th generation CPU and test the performance of bf16. I also found that the overall utilization rate of the current 96-core CPU is about 16% (30 concurrent requests). I hope that subsequent features will be incorporated to bring higher CPU utilization.

[ProExpertProg]

@bigPYJ1151 @WoosukKwon I did not want to slow down the merging of this PR but I was wondering if there's a plan to decouple the CPU backend via an additional level of abstraction to allow for choosing the backend at runtime (or startup time) as opposed to the build time. I'm guessing all calls that go to the _c pytorch extension would have to go through the worker/executor but it doesn't seem like it would be too complex?

[zhouyuan]

@bigPYJ1151 I get it, thank you! I need to find a 4th generation CPU and test the performance of bf16. I also found that the overall utilization rate of the current 96-core CPU is about 16% (30 concurrent requests). I hope that subsequent features will be incorporated to bring higher CPU utilization.

Hi @markluofd Thanks for reporting, besides the threading pool conflict issue posted by @bigPYJ1151, in CPU based env you may need to do several tunings to get better performance, especially on NUMA node access and OpenMP threads.

OMP_NUM_THREADS=32 numactl --physcpubind=0-31 --membind=0 python benchmark.py

In my 4th gen Xeon env, this tuning can bring ~30% perf improvement. I suppose this can also help to improve the resource utilization in your tests.

Here are some tuning recipe for CPU based env:
https://pytorch.org/tutorials/intermediate/torchserve_with_ipex.html https://intel.github.io/intel-extension-for-pytorch/cpu/latest/tutorials/performance_tuning/tuning_guide.html

thanks, -yuan

[bigPYJ1151]

Hi @ProExpertProg It is feasible to load different backends dylib at runtime. vLLM has multple backends with different dependencies and configurations, so it might be a lot of works to support the runtime binding.