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New daily trending repos in Verilog
New daily trending repos in Verilog!
efabless / caravel_user_project https://caravel-user-project.readthedocs.io
New daily trending repos in Verilog!
analogdevicesinc / hdl HDL libraries and projects
EttusResearch / uhd The USRP™ Hardware Driver Repository
New daily trending repos in Verilog!
ZipCPU / zipcpu A small, light weight, RISC CPU soft core +2 stars today
BrunoLevy / TordBoyau A pipelined RISC-V processor
New daily trending repos in Verilog!
pConst / basic_verilog Must-have verilog systemverilog modules +2 stars today
New daily trending repos in Verilog!
cornell-ece4750 / ece4750-sec08-mem ECE 4750 Section 8: Lab 3 Head Start
SI-RISCV / e200_opensource Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
alexforencich / verilog-ethernet Verilog Ethernet components for FPGA implementation
New daily trending repos in Verilog!
efabless / caravel Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space. +3 stars today
olofk / serv SERV - The SErial RISC-V CPU +3 stars today
lnis-uofu / OpenFPGA An Open-source FPGA IP Generator +1 stars today
nand2mario / nestang NESTang is a Nintendo Entertainment System emulator on the affordable Sipeed Tang Primer 20K FPGA board.
New daily trending repos in Verilog!
KastnerRG / riffa The RIFFA development repository +1 stars today
sudhamshu091 / 32-Verilog-Mini-Projects Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 7…
xiaop1 / Verilog-Practice HDLBits website practices & solutions
New daily trending repos in Verilog!
ultraembedded / cores Various HDL (Verilog) IP Cores +1 stars today
bespoke-silicon-group / basejump_stl BaseJump STL: A Standard Template Library for SystemVerilog
nekromant / rsensor Usonic range sensor model for Leonid.
The-OpenROAD-Project / OpenROAD-flow-scripts
New daily trending repos in Verilog!
IObundle / iob-mem Verilog behavioral description of various memories
Xilinx / libsystemctlm-soc SystemC/TLM-2.0 Co-simulation framework
New daily trending repos in Verilog!
ultraembedded / riscv RISC-V CPU Core (RV32IM) +1 stars today
alexforencich / verilog-ethernet Verilog Ethernet components for FPGA implementation
New daily trending repos in Verilog!
bu-ec311-fall2022 / EC311_Lab2_Template
odriverobotics / ODriveHardware High performance motor control
New daily trending repos in Verilog!
The-OpenROAD-Project / OpenLane OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization. +3 stars today
chipsalliance / yosys-f4pga-plugins Plugins for Yosys developed as part of the F4PGA project.
New daily trending repos in Verilog!
google / CFU-Playground Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below. +3 stars today
circuitvalley / USB_C_Industrial_Camera_FPGA_USB3 Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
New daily trending repos in Verilog!
riscv-mcu / e203_hbirdv2 The Ultra-Low Power RISC-V Core +1 stars today
s-hfarooq / ece498hk-RISCV-V-Extension +1 stars today
ashutoshaks / COA-Laboratory-CS39001 Assignments for the Computer Organization And Architecture Laboratory course
qrp73 / ali_trx Building your own SDR DDC/DUC transceiver with DIY modules from aliexpress
New daily trending repos in Verilog!
YosysHQ / picorv32 PicoRV32 - A Size-Optimized RISC-V CPU +1 stars today
nvdla / hw RTL, Cmodel, and testbench for NVDLA
New daily trending repos in Verilog!
corundum / corundum Open source FPGA-based NIC and platform for in-network compute +2 stars today
vortexgpgpu / vortex +1 stars today
New daily trending repos in Verilog!
RapidSilicon / litex_reference_designs Litex Reference Designs provides reference designs created out of IP Catalog using Litex integration capabilities.
New daily trending repos in Verilog!
alexforencich / verilog-pcie Verilog PCI express components +1 stars today
New daily trending repos in Verilog!
borti4938 / n64adv2_fw +1 stars today
The-OpenROAD-Project / OpenROAD OpenROAD's unified application implementing an RTL-to-GDS Flow
Mazamars312 / Analogue_Pocket_Neogeo Analogue Pocket Neogeo Core compatible with openFPGA
ucb-bar / nvdla-wrapper Wraps the NVDLA project for Chipyard integration
New daily trending repos in Verilog!
alexforencich / verilog-axi Verilog AXI components for FPGA implementation
New daily trending repos in Verilog!
cornell-ece4750 / ece4750-sec11-sys ECE 4750 Section 11: Lab 4 Head Start
New daily trending repos in Verilog!
nvdla / hw RTL, Cmodel, and testbench for NVDLA +1 stars today
os-fpga / FPGA_PRIMITIVES_MODELS
New daily trending repos in Verilog!
The-OpenROAD-Project / OpenROAD-flow-scripts OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/ +2 stars today
New daily trending repos in Verilog!
darklife / darkriscv opensouce RISC-V cpu core implemented in Verilog from scratch in one night! +1 stars today
calissile / statemachine-reducestate reduce state optimization
New daily trending repos in Verilog!
algofoogle / raybox-zero Minimal implementation of Raybox HDL ray caster concept +2 stars today
New daily trending repos in Verilog!
alexforencich / verilog-pcie Verilog PCI express components +3 stars today
New daily trending repos in Verilog!
The-OpenROAD-Project / OpenROAD OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
New daily trending repos in Verilog!
ufrisk / pcileech-fpga FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software +1 stars today
New daily trending repos in Verilog!
rejunity / tiny-asic-1_58bit-matrix-mul Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit +6 stars today
vertrex / Arcade-JujuDensetsu_MiSTer JuJuDensets / Toki MiSTer core +1 stars today
chipsalliance / synlig SystemVerilog support for Yosys
New daily trending repos in Verilog!
vortexgpgpu / vortex +2 stars today
riscv-mcu / e203_hbirdv2 The Ultra-Low Power RISC-V Core +1 stars today
alexforencich / verilog-uart Verilog UART
New daily trending repos in Verilog!
corundum / corundum Open source FPGA-based NIC and platform for in-network compute
chaimleib / UARTecho basic UART that retransmits its input
chipsalliance / yosys-f4pga-plugins Plugins for Yosys developed as part of the F4PGA project.
New daily trending repos in Verilog!
alexforencich / verilog-ethernet Verilog Ethernet components for FPGA implementation +4 stars today
New daily trending repos in Verilog!
IObundle / iob-cache Verilog Configurable Cache +1 stars today
IObundle / iob-picorv32 IOb_SoC version of the Picorv32 RISC-V Verilog IP core
New daily trending repos in Verilog!
YosysHQ / picorv32 PicoRV32 - A Size-Optimized RISC-V CPU +1 stars today
Xilinx / libsystemctlm-soc SystemC/TLM-2.0 Co-simulation framework +1 stars today
T-head-Semi / openc910 OpenXuantie - OpenC910 Core
splinedrive / KianV-RV32IMA-RISC-V-uLinux-SoC
New daily trending repos in Verilog!
efabless / caravel Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space. +2 stars today
New daily trending repos in Verilog!
alexforencich / verilog-axi Verilog AXI components for FPGA implementation +2 stars today
New daily trending repos in Verilog!
EttusResearch / uhd The USRP™ Hardware Driver Repository +2 stars today
xiaop1 / Verilog-Practice HDLBits website practices & solutions +1 stars today
Digital-EDA / Digital-IDE All in one vscode plugin for HDL development
New daily trending repos in Verilog!
analogdevicesinc / hdl HDL libraries and projects +1 stars today
ucb-bar / nvdla-wrapper Wraps the NVDLA project for Chipyard integration
New daily trending repos in Verilog!
circuitvalley / USB_C_Industrial_Camera_FPGA_USB3 Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source. +1 stars today
atrac17 / Toaplan2 Toaplan V2 system for MiSTerFPGA
New daily trending repos in Verilog!
pConst / basic_verilog Must-have verilog systemverilog modules +2 stars today
Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition This is the repository for the IEEE version of the book
Obijuan / open-fpga-verilog-tutorial Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
New daily trending repos in Verilog!
New daily trending repos in Verilog!
ekknod / pcileech-wifi pcileech-fpga with wireless card emulation
IObundle / iob-soc RISC-V System on Chip Template