False positive on differently shared idents

[toddstrader]

I'm running into ident mapping issues with this tool while working on: https://github.com/verilator/verilator/pull/6707

Namely:

> some.signal (%", W#) at time 0 next occurence at time 9026627

where some.signal does not differ between the VCDs.

This happens because of limitations in fd1_to_fd2_mapG / fd2_to_fd1_mapG. Mainly those lists assume that there's a 1:1 mapping between idents, but this doesn't have to be so. E.g. if foo, bar and baz are all logically equivalent, it's possible for them to have idents of a, a, a or a, b, b or a, a, b. I haven't yet reduced my example VCDs to something manageable. If / when I do, I'll post a PR with VCDs to demonstrate.

I'm not currently looking at fixing this because I realized that this is more bulletproof than the current implementation of vcddiff:

diff <(fstminer -c file_1.fst | sort) <(fstminer -c file_2.fst | sort)

It's not clear to me yet what I'm actually going to need here in order to land the Verilator PR. It's possible this issue could be resolved by making fd1_to_fd2_mapG a list of lists of ints, but I'm starting to worry that the hole is deeper than that.

Anyway, mostly an FYI for now.

[wsnyder]

A simple test of changing only ident compares correctly for me, if you find a test case that breaks please note it and/or pull to fix.