vtr-verilog-to-routing
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Published
20 hours ago •
verilog-to-routing
verilog-to-routing
[Packer] Setting Higher Target Pin Utilization When Regions are Full
The packer currently has a fallback where, if it could not pack after 4 iterations, it will increase the target pin utilization of the clusters to give it a better chance of finding a valid clustering (at the expense of runtime): https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/e38c0f3d975decbafc112d18877a99506c7e845f/vpr/src/pack/pack.cpp#L195-L208
As the TODO reads, this was implemented in a very hard-coded way. It assumes the logic block type which was having issues is the clbs and the name is "clb".
This should either increase the target pin utilization for the overused block types or it should just increase the target pin utilization for all logical block types.
