vtr-verilog-to-routing
vtr-verilog-to-routing copied to clipboard
[WIP] Router Lookahead Profiler
There is a new class LookaheadProfiler
which records a variety of data that can be used to evaluate the quality of the router lookahead.
Description
Using the branch reconstructed in RouteTree::add_subtree_from_heap()
, LookaheadProfiler
records the following data into a .csv
file for every node in the branch:
- iteration no.
- source node id (the first node in the branch; not necessarily a SOURCE)
- sink node id
- sink block name
- sink atom block model
- sink cluster block type
- sink cluster tile height
- sink cluster tile width
- current node
- node type
- node length
- num. nodes from sink
- delta x, delta y
- actual cost, delay, and congestion from current node to sink
- predicted cost, delay, and congestion from current node to sink (predicted by the lookahead)
- criticality
The profiler is enabled by specifying CMAKE_PARAMS="DVPR_PROFILE_LOOKAHEAD=on"
when building VPR, and also using the command-line option --profile_router_lookahead [output_file_name.csv]
.
This data can be analyzed using the script vtr_flow/scripts/profiling_utils/parse_lookahead_data.py
, which produces a data summary file and a number of scatter plots, bar graphs, pie charts, and heatmaps. (TBD: Currently, using -h
gives detailed instructions, but a README will be added as well.)
Motivation and Context
This was used to verify issues that led to #2639. It can be used to identify current/future issues with the lookahead.
How Has This Been Tested?
There is a new CI test that ensures that VPR builds properly with PROFILE_LOOKAHEAD
defined.
Currently, even with PROFILE_LOOKAHEAD
undefined, there is a degradation in QoR. These results are averages over 3 runs each:
Routing Runtime (s) | CPD (ns) | Wirelength | Memory Footprint | |
---|---|---|---|---|
vtr (old) |
0.94 | 10.00 | 27433.36 | 153.79 |
vtr (new) |
0.91 | 10.00 | 27520.35 | 153.59 |
titan (old) |
294.51 | 17.18 | 3200094.23 | 5494.64 |
titan (new) |
294.30 | 17.48 | 3252463.91 | 5486.61 |
titan_large * (old) |
618.20 | 17.72 | 6430833.54 | 8865.55 |
titan_large * (new) |
614.95 | 18.14 | 6532452.49 | 8854.25 |
For some reason, there is a 1.6% wirelength increase on titan
(and titan_large
) circuits and a 2.4% CPD increase on titan_large
circuits.
*10 largest titan
circuits.
Types of changes
- [ ] Bug fix (change which fixes an issue)
- [x] New feature (change which adds functionality)
- [ ] Breaking change (fix or feature that would cause existing functionality to change)
Checklist:
- [x] My change requires a change to the documentation
- [ ] I have updated the documentation accordingly
- [x] I have added tests to cover my changes
- [ ] All new and existing tests passed