vtr-verilog-to-routing
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Published
20 hours ago •
verilog-to-routing
verilog-to-routing
Placement `channel_width_fac`
Throughout the placement code, we need to frequently use min and max functions in time-sensitive parts of the code before accessing channel_width_fac. This data structure should be updated to cover the entire grid (from 0 to width-1, and so on). During the pre-computation of the inverse of the average channel width, we can assume that the channel width at width-1 is the same as the channel width at width-2. This change would simplify the code, remove an asymmetry that is no longer necessary, and might slightly speed up the code.
