vtr-verilog-to-routing
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verilog-to-routing
NoC-aware packing optimization and NoC-biased centroid move type
The packing algorithm may infer logical connectivity through high-fanout nets like reset and clock enable, especially in NoC designs. This could lead to atoms from unconnected modules being packed together. Once this happens, more atoms from the unconnected module can join through low-fanout nets. Placing such clustered blocks is challenging because they are connected (not necessarily directly) to NoC routers, but NoC routers are usually very far from each other. As a results, clustered blocks of two unconnected modules are stretched between two NoC routers. To address this, we use BFS on the atom netlist to identify connected components including NoC routers. Once identified, we prevent atoms from different components from clustering together.
In the placement stage, a new move type is introcuded: NoC-baised centroid. After the centroid loaction of a clustered block is computed, it is adjusted towards its reachable NoC routers. To find reachable NoC routers for all blocks, we run BFS on the clustered netlist to find connected components containing NoC routers.
This PR is submitted for code review. QoR results for the initial implementation of this PR are available in the paper. QoR results for the current version will be added soon.
Types of changes
- [ ] Bug fix (change which fixes an issue)
- [x] New feature (change which adds functionality)
- [ ] Breaking change (fix or feature that would cause existing functionality to change)
Checklist:
- [ ] My change requires a change to the documentation
- [ ] I have updated the documentation accordingly
- [ ] I have added tests to cover my changes
- [ ] All new and existing tests passed
