Failed routing due to unusable stratix10_arch.xml

[OlinLai]

When I try to run vtr_flow or vtr_task, regardless of the circuit I choose (e.g. blink.v), as long as the FPGA architecture is stratix10_arch.xml, I always encounter an error (seems to be a routing failure) in the end.

Expected Behaviour

It should be successful.

Current Behaviour

stratix10_arch/blink            Error: Executable vpr failed
        full command:  /usr/bin/env time -v /root/vtr-verilog-to-routing/vpr/vpr stratix10_arch.xml blink --circuit_file blink.pre-vpr.blif
        returncode  :  134
        log file    :  /root/vtr-verilog-to-routing/Bsweep/temp/vpr.out
failed: Executable vpr failed (took 0.73 seconds, overall memory peak 60.35 MiB consumed by vpr run)

and I attached vpr.out vpr.out.txt

Possible Solution

Steps to Reproduce

run command like below

$VTR_ROOT/vtr_flow/scripts/run_vtr_flow.py \
  $VTR_ROOT/doc/src/quickstart/blink.v \
  $VTR_ROOT/vtr_flow/arch/COFFE_22nm/stratix10_arch.xml

Context

I would like to make some modifications to the Stratix 10 architecture to observe various metrics of applications on the optimized architecture (e.g., number of used resources). For this, I need stratix10_arch.xml as a baseline.

Your Environment

• VTR revision used: git clone master on 2023/12/10
• Operating System and version: Fedora release 29
• Compiler version: gcc 11.2.0