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Published 20 hours ago • verified publisher icon verilog-to-routing

flat routing makes graphics crash

Open vaughnbetz opened this issue 1 year ago • 1 comments

When flat routing is enabled, the graphics crash with an assertion if you set --disp on

Expected Behaviour

Short term: give an unsupported option combination error Longer term: make it work.

Current Behaviour

Steps to Reproduce

  1. Run the vpr router with --flat_routing true --disp on
  2. Select Net Settings | prim neist.
  3. Quartus will crash with an assertion: /homes/v/vaughn/ece1756/2023/lab4/vtr-verilog-to-routing/vpr/src/draw/draw_rr_edges.cpp:472 draw_pin_to_chan_edge: Assertion '1 < pin_candidate_sides.size()' failed.

Context

Can't turn on graphics for ECE 1756 assignment with flat routing.

Your Environment

  • VTR revision used: mid-Nov. 2023 master
  • Operating System and version: Linux

vaughnbetz avatar Nov 28 '23 22:11 vaughnbetz

This issue is addressed in PR #2524

amin1377 avatar Apr 02 '24 15:04 amin1377