vtr-verilog-to-routing
vtr-verilog-to-routing copied to clipboard
verilog-to-routing
Congestion placement
Description
This change adds a congestion aware placement into vpr. This algorithm takes advantage of the crossing parameter in VPR to make the congestion matrix and adds it into the placement cost function.
Related Issue
Motivation and Context
Since VPR does not support congestion in placement, The final placement sometimes is unroutable. Therefore, this chagne help VPR to make a uncogested placement
How Has This Been Tested?
This new placer have been tested for a bunch of test-benches which were not routable via conventional SA placement algorithm.
Types of changes
- [ ] Bug fix (change which fixes an issue)
- [x] New feature (change which adds functionality)
- [ ] Breaking change (fix or feature that would cause existing functionality to change)
Checklist:
- [ ] My change requires a change to the documentation
- [ ] I have updated the documentation accordingly
- [ ] I have added tests to cover my changes
- [x] All new and existing tests passed
Adding @saaramahmoudi and @soheilshahrouz as reviewers as they know this code. @behnam-rs : you should have an invite to the vtr repositories in your email; if you accept it CI will start running automatically when you push code or make a pull request.
@behnam-rs Is there any specific reason that you want to merge this into openfpga branch instead of the master? From what I saw in the code, there is nothing specific to TILEABLE feature and only the place engine changed.
