vtr-verilog-to-routing
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Openfpga
Description
We made analytical placer timing-driven and added options to VPR to use it as an initial placer before SA Placer.
Related Issue
Motivation and Context
It makes SA placer more stable and leads to better QoR.
How Has This Been Tested?
We have bee tested via our benchmark set,
Types of changes
- [ ] Bug fix (change which fixes an issue)
- [x] New feature (change which adds functionality)
- [ ] Breaking change (fix or feature that would cause existing functionality to change)
Checklist:
- [ ] My change requires a change to the documentation
- [ ] I have updated the documentation accordingly
- [ ] I have added tests to cover my changes
- [x] All new and existing tests passed