vtr-verilog-to-routing
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[WIP] Parallel router: net decomposition
Based on #2357. Contains the ongoing work on the parallel router to improve thread utilization.
Description
Related Issue
Motivation and Context
How Has This Been Tested?
Types of changes
- [ ] Bug fix (change which fixes an issue)
- [ ] New feature (change which adds functionality)
- [ ] Breaking change (fix or feature that would cause existing functionality to change)
Checklist:
- [ ] My change requires a change to the documentation
- [ ] I have updated the documentation accordingly
- [ ] I have added tests to cover my changes
- [ ] All new and existing tests passed
Rebased this on master: most of the fixes are backported to #2357, which is going to be squashed and rebased too.
Planning to keep this branch as "code storage", divide the changes into a few PRs and do some refactoring in the process. Can rebase this branch as the smaller PRs are merged.