vtr-verilog-to-routing
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add top module and search path for parmys
Fix temp_dir parse error and add features for Yosys+Parmys
Description
This PR fixed the issue for #2347, which may cause Parmys+Yosys synthesize failure.
This PR also adds two features for #2351
Since the VTR project moves to Parmys+Yosys front end, more people are likely to write projects using SystemVerilog and use the include
syntax to organize projects, so I added the command line support for letting Yosys search for the include
directory.
In addition, I added support for manually specifying the top module for Yosys, in case sometimes Yosys find the wrong top module hierarchy.
Related Issue
#2347 #2351
Motivation and Context
I am doing my project with VTR and using SystemVerilog as my main language, so I added the two features to support wider use.
How Has This Been Tested?
Tested on Ubuntu 22.04 LTS.
Types of changes
- [x] Bug fix (change which fixes an issue)
- [x] New feature (change which adds functionality)
- [ ] Breaking change (fix or feature that would cause existing functionality to change)
Checklist:
- [x] My change requires a change to the documentation
- [ ] I have updated the documentation accordingly
- [ ] I have added tests to cover my changes
- [x] All new and existing tests passed
The
-top
seems to exist in the document https://docs.verilogtorouting.org/en/latest/parmys/parmys_plugin/, but was not supported in the command line, so I added this. The include dir needs a documentation change to let people know this feature.