vtr-verilog-to-routing
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Synthesis failing on included arch and benchmarks
Synthesis is failing on some VTR benchmarks, such as diffeq1.v and diffeq2.v when targeting some of the included architectures.
Steps to Reproduce
If you attempt to synthesize diffeq1.v with arch k6_N10_40nm.xml, like so:
$VTR_ROOT/vtr_flow/scripts/run_vtr_flow.py \
$VTR_ROOT/vtr_flow/benchmarks/diffeq1.v \
$VTR_ROOT/vtr_flow/arch/timing/k6_N10_40nm.xml \
-start parmys -end abc \
-top_module diffeq_paj_convert \
-temp_dir full_path_to_temp_dir
synthisis will fail, and the tail of parmys.out will read:
24.10. Finished OPT passes. (There is nothing left to do.)
25. Starting parmys pass.
ERROR: BUF_NODE
Command exited with non-zero status 1
Command being timed: "/home/ept/tools/vtr-verilog-to-routing/build/bin/yosys -c synthesis.tcl"
User time (seconds): 0.06
System time (seconds): 0.00
Percent of CPU this job got: 98%
Elapsed (wall clock) time (h:mm:ss or m:ss): 0:00.07
Average shared text size (kbytes): 0
Average unshared data size (kbytes): 0
Average stack size (kbytes): 0
Average total size (kbytes): 0
Maximum resident set size (kbytes): 31608
Average resident set size (kbytes): 0
Major (requiring I/O) page faults: 0
Minor (reclaiming a frame) page faults: 4274
Voluntary context switches: 1
Involuntary context switches: 8
Swaps: 0
File system inputs: 0
File system outputs: 24
Socket messages sent: 0
Socket messages received: 0
Signals delivered: 0
Page size (bytes): 4096
Exit status: 1
This does NOT happen if you use arch EArch.xml instead. This problem arrises with a number of benchmarks when using k6_N10_40nm.xml (and others), but not with all benchmarks. For example, stereovision0.v works fine with k6_N10_40nm.xml.
Your Environment
- VTR revision used: f2783e2f8c7531d00fa3e857ee22d1c45f975815
- Operating System and version: Ubuntu 20.04.5 LTS
- Compiler version: gcc version 9.4.0 (Ubuntu 9.4.0-1ubuntu1~20.04.1)
This may be related to #2302, but I'm specifying the full path to the temp_dir so that isn't the problem/solution.