Allow for graphical representation of an architecture without having to build and implement a design

[WhiteNinjaZ]

It would be nice if there was a way to graphically view how an architecture definition is laid out without having to create and implement a design.

Proposed Behaviour

Allow vtr graphics to be run on an architecture definition instead of just on a net-list so that general layout of CLB's, carry, RAM, etc, can be checked for correctness. It might also be nice to be able to view a graphical representation of individual pieces of an architecture (i.e. CLB's) without all of the routing or other parts of the design.

Current Behaviour

VTR graphics can only be run on an implemented design.

Possible Solution

One solution that works with the current software is to write a simple design and implement it using VTR. However, the proposed functionality above would allow for greater flexibility as well as the ability to build an architecture in incremental steps more easily.

Context

I have been working on implementing architecture definitions for the Xilinx7 series and it would be nice to be able to visualize what I am doing in xml. I can make a simple design and run it through the flow in graphics mode but it is a little difficult to do things in incremental steps (i.e. an architecture must have switch blocks and internal logic before a visual representation of the architecture can be shown). It would be nice to view the internals of a single CLB I am working on without having to design an entire arch file and a verilog design and then run it through the flow.