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Published 20 hours ago • verified publisher icon verilog-to-routing

post synthesis netlist bug

Open ghost opened this issue 2 years ago • 0 comments

I generated a counter netlist using VTR flow and vpr. VPR 8.1.0 generates all LUT inputs as 1'bX unlike VPR 8.0.0 in "counter_post_synthesis.v". Reproducing: $VTR_ROOT/vtr_flow/scripts/run_vtr_flow.py $VTR_ROOT/doc/src/quickstart/counter.v $VTR_ROOT/vtr_flow/arch/timing/EArch.xml -temp_dir . --route_chan_width 100 $VTR_ROOT/vpr/vpr $VTR_ROOT/vtr_flow/arch/timing/EArch.xml counter.pre-vpr.blif --gen_post_synthesis_netlist on So behavioral simulation is not working. When I change all 1'bX's to 1'b0's in post_synthesis_netlist, simulation works correctly. Netlist file is attached below.

up_counter_post_synthesis.txt

ghost avatar Mar 29 '22 06:03 ghost