vtr-verilog-to-routing
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verilog-to-routing
WIP: Edge switch subsets
Overview
This folding method is represented in the image below and is the most compact representation explored thus far. This branch is still very much a work in progress, but I am looking for advice on how to optimize my implementation. As a reminder, this implementation only works if the RRGraph is read from a file.
Relevant Code Snippets
The following code snippets are places in the implementation that have great impact on its performance. If there are any ways to optimize these snippets, performance would benefit greatly.
Data structures used to implement RRGraph
https://github.com/ethanroj23/vtr-verilog-to-routing/blob/cd0d1716305b40a76253630f99f3294f69512abe/vpr/src/route/rr_graph_storage.h#L924-L943
This function fills a vector with a node's edges. Perhaps this could be replaced with iterators?
https://github.com/ethanroj23/vtr-verilog-to-routing/blob/cd0d1716305b40a76253630f99f3294f69512abe/vpr/src/route/rr_graph_storage.h#L402-L423
Primary access of edges in the router
https://github.com/ethanroj23/vtr-verilog-to-routing/blob/cd0d1716305b40a76253630f99f3294f69512abe/vpr/src/route/connection_router.cpp#L424-L467
Primary access of edges in lookahead
https://github.com/ethanroj23/vtr-verilog-to-routing/blob/cd0d1716305b40a76253630f99f3294f69512abe/vpr/src/route/router_lookahead_map.cpp#L650-L718
@ethanroj23 Would you mind resolving the merging conflicts before I start code review? If you need help, just let me know.
