How VPR calculate delay using RC parameters?

[boldasl]

Hi. Thank you for making VPR. It's very useful.

How does VPR calculate (channel) delay using Cin, Cout, R, Rmetal and Cmetal parameters in switch and segment tag? I wonder how VPR models the physical characteristics of FPGA and how it calculates the timing report.

 <switchlist>
    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist>
<segmentlist>
  <segment freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
    <mux name="0"/>
    <sb type="pattern">1 1 1 1 1</sb>
    <cb type="pattern">1 1 1 1</cb>
  </segment>
</segmentlist>

When calculating the channel delay, is it calculated like Total (channel) delay = Tdel + Requivalent * Cequivalent ? In this case, how can we determine the Requivalent and Cequivalent?

#Path 1
Startpoint: a.inpad[0] (.input at (7,0) clocked by virtual_io_clock)
Endpoint  : out:c.outpad[0] (.output at (5,0) clocked by virtual_io_clock)
Path Type : setup

Point                                                             Incr      Path
--------------------------------------------------------------------------------
clock virtual_io_clock (rise edge)                               0.000     0.000
clock source latency                                             0.000     0.000
input external delay                                             0.000     0.000
a.inpad[0] (.input at (7,0))                                     0.000     0.000
| (intra 'io' routing)                                           0.042     0.042
| (OPIN:5017 side: (TOP,) (7,0))                                 0.000     0.042
| (CHANX:10886 L4 length:4 (7,0)->(4,0))                         0.142     0.185
| (IPIN:4205 side: (BOTTOM,) (6,1))                              0.072     0.257
| (intra 'clb' routing)                                          0.095     0.352
c.in[0] (.names at (6,1))                                        0.000     0.352
| (primitive '.names' combinational delay)                       0.261     0.613
c.out[0] (.names at (6,1))                                       0.000     0.613
| (intra 'clb' routing)                                          0.025     0.638
| (OPIN:4252 side: (RIGHT,) (6,1))                               0.000     0.638
| (CHANY:12459 L4 length:4 (6,1)->(6,4))                         0.149     0.787
| (CHANX:11044 L4 length:4 (6,2)->(3,2))                         0.142     0.929
| (CHANY:12300 L4 length:2 (4,2)->(4,1))                         0.099     1.028
| (CHANX:10889 L4 length:4 (5,0)->(8,0))                         0.142     1.170
| (IPIN:3362 side: (TOP,) (5,0))                                 0.072     1.242
| (intra 'io' routing)                                           0.014     1.256
out:c.outpad[0] (.output at (5,0))                               0.000     1.256
data arrival time                                                          1.256

clock virtual_io_clock (rise edge)                               0.000     0.000
clock source latency                                             0.000     0.000
clock uncertainty                                                0.000     0.000
output external delay                                            0.000     0.000
data required time                                                         0.000
--------------------------------------------------------------------------------
data required time                                                         0.000
data arrival time                                                         -1.256
--------------------------------------------------------------------------------
slack (VIOLATED)                                                          -1.256