xc6vlx240tff1156.xml not supported?

[alainlou]

Expected Behaviour

I would expect that the provided .xml architecture definitions should work?

Current Behaviour

/usr/bin/env time -v /home/az2lou/Code/vtr-verilog-to-routing/vpr/vpr xc6vlx240tff1156.xml add8 --circuit_file add8.pre-vpr.blif --route_chan_width 20 --max_router_iterations 150
Error 1: xc6vlx240tff1156.xml:-1 <pb_type> 'DUMMY' timing-annotation/<model> mismatch on port 'cin' of model 'adder', input port 'cin' has combinational connections to port 'cout'; specified in model, but no combinational delays found on pb_type
VPR FPGA Placement and Routing.
Version: 8.1.0-dev+d58f993d0
Revision: v8.0.0-4635-gd58f993d0
Compiled: 2021-09-29T20:54:23
Compiler: GNU 7.5.0 on Linux-4.15.0-156-generic x86_64
Build Info: release IPO VTR_ASSERT_LEVEL=2

University of Toronto
verilogtorouting.org
[email protected]
This is free open source code under MIT license.

VPR was run with the following command-line:
/home/az2lou/Code/vtr-verilog-to-routing/vpr/vpr xc6vlx240tff1156.xml add8 --circuit_file add8.pre-vpr.blif --route_chan_width 20 --max_router_iterations 150


Architecture file: xc6vlx240tff1156.xml
Circuit name: add8

# Loading Architecture Description
# Loading Architecture Description took 0.01 seconds (max_rss 14.9 MiB, delta_rss +1.7 MiB)
The entire flow of VPR took 0.01 seconds (max_rss 14.9 MiB)
Command exited with non-zero status 1
	Command being timed: "/home/az2lou/Code/vtr-verilog-to-routing/vpr/vpr xc6vlx240tff1156.xml add8 --circuit_file add8.pre-vpr.blif --route_chan_width 20 --max_router_iterations 150"
	User time (seconds): 0.01
	System time (seconds): 0.00
	Percent of CPU this job got: 81%
	Elapsed (wall clock) time (h:mm:ss or m:ss): 0:00.02
	Average shared text size (kbytes): 0
	Average unshared data size (kbytes): 0
	Average stack size (kbytes): 0
	Average total size (kbytes): 0
	Maximum resident set size (kbytes): 17404
	Average resident set size (kbytes): 0
	Major (requiring I/O) page faults: 0
	Minor (reclaiming a frame) page faults: 883
	Voluntary context switches: 1
	Involuntary context switches: 22
	Swaps: 0
	File system inputs: 0
	File system outputs: 8
	Socket messages sent: 0
	Socket messages received: 0
	Signals delivered: 0
	Page size (bytes): 4096
	Exit status: 1

Possible Solution

Not sure ...

Steps to Reproduce

1. clone this repo
2. make
3. run python3 $VTR_ROOT/vtr_flow/scripts/run_vtr_flow.py add8.v $VTR_ROOT/vtr_flow/arch/timing/xc6vlx240tff1156.xml -temp_dir . --route_chan_width 20 with add8.v

module add8 #
(
    parameter WIDTH=8
)
(
    input [WIDTH-1:0] in1,
    input [WIDTH-1:0] in2,
    output [WIDTH-1:0] out
);
    assign out = in1 + in2;
endmodule

Context

I'm just trying to get started with VTR for FPGA architecture investigation :)

Your Environment

• VTR revision used: 8.1.0-dev+d58f993d0
• Operating System and version: Ubuntu 18.04.6 LTS
• Compiler version: gcc version 7.5.0 (Ubuntu 7.5.0-3ubuntu1~18.04)