C++ compile error on incorrect assignment to clocking in virtual interface

[solomatnikov]

In file included from Vt_clocking_virtual__ALL.cpp:4:
Vt_clocking_virtual___024root__DepSet_haedc89e0__0.cpp: In function ‘VlCoroutine Vt_clocking_virtual___024root___eval_initial__TOP__Vtiming__0(Vt_clocking_virtual___024root*)’:
Vt_clocking_virtual___024root__DepSet_haedc89e0__0.cpp:113:21: error: cannot convert ‘VlQueue<unsigned char>’ to ‘CData’ {aka ‘unsigned char’} in assignment
  113 |         = vlSelfRef.t__DOT__main1__DOT__data;
      |           ~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
      |                     |
      |                     VlQueue<unsigned char>

VCS:

Error-[NYI] Not Yet Implemented
testbench.sv, 46
  Feature is not yet supported: Variable sized array not supported on the 
  right-hand side of this statement
  Source info: t.mod1.cb.out <= data;                 


Error-[ICTA] Incompatible complex type
testbench.sv, 46
  Incompatible complex type assignment
  Type of source expression is incompatible with type of target expression. 
  Mismatching types cannot be used in assignments, initializations and 
  instantiations. The type of the target is 'logic', while the type of the 
  source is 'logic$[]'.
  Source Expression: data

Can you attach an example that shows the issue? (Must be openly licensed, ideally in test_regress format.)

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2024 by Antmicro Ltd.
// SPDX-License-Identifier: CC0-1.0

interface Iface;
   logic clk = 1'b0, inp = 1'b0, io = 1'b0, out = 1'b0, out2 = 1'b0;
   clocking cb @(posedge clk);
       input #7 inp;
       output out;
       inout io;
   endclocking
   always @(posedge clk) inp <= 1'b1;
   always #5 clk <= ~clk;
   assign out2 = out;
endinterface

module main;
   logic            data[];
   initial begin
      #6;
      t.mod1.cb.io <= 1'b1;
      t.mod1.cb.out <= 1'b1;
      if (t.mod0.io != 1'b0) $stop;
      if (t.mod1.cb.io != 1'b0) $stop;
      if (t.mod1.cb.inp != 1'b0) $stop;
      @(posedge t.mod0.io)
      if ($time != 15) $stop;
      if (t.mod0.io != 1'b1) $stop;
      if (t.mod1.cb.io != 1'b0) $stop;
      #1
      if (t.mod0.cb.io != 1'b1) $stop;
      if (t.mod1.cb.io != 1'b1) $stop;
      if (t.mod1.cb.inp != 1'b1) $stop;
      #8;
      t.mod0.inp = 1'b0;
      if (t.mod0.cb.inp != 1'b1) $stop;
      @(t.mod1.cb)
      if ($time != 25) $stop;
      if (t.mod0.cb.inp != 1'b1) $stop;
      t.mod0.inp = 1'b0;
      @(t.mod0.cb)
      if ($time != 35) $stop;
      if (t.mod0.cb.inp != 1'b0) $stop;
      t.mod1.cb.out <= data;
      $write("*-* All Finished *-*\n");
      $finish;
   end
   initial begin
      @(posedge t.mod0.out)
      if ($time != 15) $stop;
      if (t.mod1.out2 != 1'b1) $stop;
   end
endmodule

module t;
   main main1();
   Iface mod0();
   virtual Iface mod1 = mod0;
endmodule

What 'verilator' command line do we use to run your example?

verilator --prefix Vt_clocking_virtual --make gmake --x-assign unique -cc -Mdir obj_vlt/t_clocking_virtual --fdedup --debug-check --comp-limit-members 10 --exe --main --timing --clk clk  -f input.vc +define+TEST_OBJ_DIR=obj_vlt/t_clocking_virtual +define+TEST_DUMPFILE=obj_vlt/t_clocking_virtual/simx.vcd t/t_clocking_virtual.v

What 'verilator --version' are you using? Did you try it with the git master version?

v5.026-g34e37d7bd

What OS and distribution are you using?

Linux 5.14.0-427.24.1.el9_4.x86_64

[wsnyder]

Thanks for the report. From this and other virtual interface issues these may take some time to get to resolved, so pull requests to fix these welcome.