Vishal Canumalla

Codegen Test Macro

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Aims to solve issue #34 at least partially. Currently in stage of rewriting the tests, and adding additional cases for the macro to cover. Still needs a good amount of...

add Xilinx Virtex Architecture Description and DSP48E1

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This PR will be opened when the following is complete. The DSP48E1 is already in lakeroad-private, but we also need to do the following - [x] Create new architecture description...

Creates a tutorial for adding a new architecture description using the Xilinx Virtex and DSP48E1 platform and primitive as an example.

Add support for arbitrary width dsp operations

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This PR adds initial support for arbitrary size DSP operations (for example, a 36 bit addition). - [x] Add support for wide logical operations (AND, OR, etc.) - [x] Add...

Adding CFGLUT5 primitive

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This PR aims to add support for the CFGLUT5 primitive. Closes #259 See: https://github.com/uwsampl/lakeroad-private/pull/1

Currently, `lr:var` can be instantiated with symbols or strings as their names. This can cause a number of issues. In my experience, this manifested in this way. When I tried...