lakeroad
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uwsampl
FPGA synthesis tool powered by program synthesis
- Sometimes multiplications need to be rewritten so that the solver can deal with them. I think this was a problem with the Intel multiplier. - Sometimes you must make...
We likely slowed down imported semantics in #265 . We need some ways to make them faster. - Subexpression sharing?
- Lattice ALU54B model has an `always` block that is missing a signal in its sensitivity list. This was found when updating things to use `always_comb`. See https://github.com/uwsampl/lakeroad-private/blob/ac9fdc6877873c74a7323f7de7ce13b09e3f3e01/lattice_ecp5/modified_ALU54B.v#L1951. I think...
See https://github.com/uwsampl/lakeroad/issues/161#issuecomment-1464853392 See #198 See #199
Implement optimizations for each instruction so that we beat all existing tools in the three big tables in the paper. There are a bunch of PRs that relate to specific...
This is an overarching issue to track the larger task of supporting the CFGLUT5 primitive. Tasks: - [ ] Import semantics - [ ] Add initial sketch for proof of...
This would be a significant project. Can we use Lakeroad to synthesize a DSP + a memory with instructions to be read? Can we make it compute something interesting?
See commit message on commit [b854805](https://github.com/uwsampl/lakeroad/commit/b854805cfaee474dc02fe67bbf72a4d67675b6bd)
Currently, Lakeroad does not differentiate between signed and unsigned numbers. Given that there are no bitvector operators directly supported in the Lakeroad language, this makes sense in theory -- each...