lakeroad
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uwsampl
FPGA synthesis tool powered by program synthesis
Ideally this would be doable via an `include`, but I'm not sure that'll be possible as long as we have custom primitives that need to be added via Rust.
https://arxiv.org/abs/2304.10646 Rachit and I have talked about this a good deal. Filament's module interfaces provide information that Lakeroad needs: the number of clock cycles before output is expected, plus information...
They're just a similar pattern repeated over and over again. Could write code to generate them automatically.
Convert from language in `lakeroad.egg` to language in `lakeroad-antiunify.egg`
In my [generals talk](https://www.youtube.com/watch?v=M8i2HKEnoqI), I proposed deduplicating "instructions" from a hardware design using a set of rewrites: The rewrites looked like, e.g.: ``` (binop ?op ?bw (apply (instr ?ast0 ?canonical-args0)...
This PR adds initial support for arbitrary size DSP operations (for example, a 36 bit addition). - [x] Add support for wide logical operations (AND, OR, etc.) - [x] Add...
This PR aims to add support for the CFGLUT5 primitive. Closes #259 See: https://github.com/uwsampl/lakeroad-private/pull/1
I'm trying to cleanup outstanding PRs pre paper release. See notes in the PR about the minimal effort we need to close: #249