Defaulting to symbolic values in the verilog->racket turns out to be a bad idea

[gussmith23]

It's bad because, when we call the generated functions when doing synthesis, they introduce symbolic variables that don't necessarily end up in the overarching Lakeroad expression. That is, a Lakeroad expression like:

(hw-module
  "my_module"
  (list some-port some-other-port)
  ...)

will trigger the interpreter for "my_module". If not all of the ports are specified, those ports will have symbolic values, which the solver can solve for to make synthesis work. However, these solved values do not end up in the hw-module expression, and thus won't get compiled. I ran into this when I didn't specify every single port and parameter for CCU2C in the lattice config. It was a nasty bug to track down.

The practical solution for this for now is to always specify every port and every parameter in the config.