SystemVerilog: "assertions" parsing error when encountered "::"

[roccomao]

The name of the parser: Verilog/SystemVerilog

In many cases, when defining an assertion (assert, assume, cover, restrict), there is no explicit naming label. If there are other uncovered or exposed (not parsed by other tags) colons before it, it will be detected as an assertion. For example:

import uvm_pkg::*;
// something
assert (foo) else do something;
// something
someclass::method();
// something
assert (bar) else do something;

Output tags as follow:

uvm_pkg	input.sv	/^assert (foo) else do something;$/;"	A
someclass	input.sv	/^assert (bar) else do something;$/;"	A

This is not the expected result. Expected should be empty.