Scheduling commands

[taehyunzzz]

Hello, I have an issue with RW command scheduling.

I am using a DDR3 configuration with transaction queue size of 32 and command queue size of 32. While running simulation, there came a point where both read and write queues were full i.e. size 32. From this point on, no R/W command could be issued due to and alleged read-before-write dependency.

I found that ScheduleTransaction() in src/controller.cc seems to be the issue. When a RW dependency is found, write_draining is set to 0 here so that a read command could be issued. However, in the next call to this function, this line of code sets the variable back to 32, leading to issuance of a write command. In a nutshell, write command is stalled until read command(s) with RW dependency is issued out, whereas no read command is ever issued because write_draining is never 0, forming a deadlock situation.

To my understanding, this conditional gives write commands a priority over read commands. My problem seems to be caused from this scheduling policy.

My question is, does it make sense to change this policy in DRAM or is DRAM scheduling always implemented as the above (using 'write draining')? Is it safe to change this conditional a bit, say for line 201, if ((write_buffer_.size() == write_buffer_.capacity()-1) || ?

Thanks for the great work, by the way.