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Published 20 hours ago • verified publisher icon umarcor
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Open Source Verification Bundle for VHDL and System Verilog

'Doc' workflow status 'Test' workflow status

Frameworks and methodologies

Simulators/compilers

Proofs of concept

pyCAPI

Open Source VHDL Design Explorer (OSVDE)

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verified publisher icon umarcor

Metadata

Open Source Verification Bundle for VHDL and System Verilog

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