osvb
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Open Source Verification Bundle for VHDL and System Verilog
Frameworks and methodologies
- Coroutine Co-simulation Test Bench (cocotb)
- Open Source VHDL Verification Methodology (OSVVM)
- SVUnit
- Universal VHDL Verification Methodology (UVVM)
- VUnit
Simulators/compilers
Proofs of concept
pyCAPI
Open Source VHDL Design Explorer (OSVDE)
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