Unai Martinez-Corral
Unai Martinez-Corral
- https://github.com/chipsalliance/f4pga-examples/blob/main/docs/building-examples.rst uses a toctree to import files from https://github.com/chipsalliance/f4pga-examples/tree/main/docs/xc7 - See for instance the litex sata demo: https://github.com/chipsalliance/f4pga-examples/blob/main/docs/xc7/litex_sata_demo.rst - As a result, https://github.com/chipsalliance/f4pga-examples/blob/main/xc7/litex_sata_demo/README.rst is processed through the template in...
Close #362.
This PR moves the content of chipsalliance/yosys-f4pga-plugins to this repo as subdir `yosys-plugins`.
Follow-up of #613.
As commented in #3, container images including irsim were added to [hdl/containers](https://github.com/hdl/containers). Before updating the images, we run some quick tests on them to ensure that the tools were successfully...
Last year, container images including magic were added to [hdl/containers](https://github.com/hdl/containers) (hdl/containers#27). As of today, images including irsim are available as well (hdl/containers#30). Both magic and irsim are available on amd64,...
[VHDL/pyVHDLModel](https://github.com/VHDL/pyVHDLModel) is an abstract language model for VHDL, meant to be used as an interface between *any* VHDL parser and projects providing graphical views, reformatted output, documentation, etc. A currently...
During the last weeks, some PRs were proposed with regard to building and packaging icesprog (#16, #17, #18, #19). I'm glad to tell that icesprog is now available in official...