Unai Martinez-Corral

I forked this repo to github.com/hdl as well: [hdl/pyHDLParser](https://github.com/hdl/pyHDLParser). Let's continue the discussion in hdl/pyHDLParser#1.

It is! Congrats @nobodywasishere! In https://github.com/buildthedocs/docker we have some dockerfiles for having container images for documentation purposes. Those are used in GHDL, VUnit, [btd](https://github.com/buildthedocs/btd), [rodrigomelo9/FOSS-for-FPGAs](https://github.com/rodrigomelo9/FOSS-for-FPGAs), etc. We might add one...

@nobodywasishere, this repo is in SymbiFlow's organisation, which is lead by @mithro. One of his mottos is "publish fast and improve later; publish even before you think you are ready"....

@nobodywasishere. try with `shell=False`. I tried the following: ```py #!/usr/bin/env python3 import subprocess as sp print('First') print(sp.check_output(['yosys', '--version'], shell=True).decode("utf-8")) print('Second') print(sp.check_output('yosys --version', shell=True).decode("utf-8")) print('Third') print(sp.check_output(['yosys', '--version'], shell=False).decode("utf-8")) print('Fourth') print(sp.check_output('yosys --version',...

> What errors were you running into using it as it is? This is running `make -C docs html` on branch https://github.com/umarcor/sphinxcontrib-hdl-diagrams/commits/make/msys2: ``` ... reading sources... [100%] index looking for...

My very quick reaction (before going through the details of your message) is: That's one of @Paebbels' main goals since years. As you can see in [Paebbels/pyVHDLParser: Use Cases](https://github.com/Paebbels/pyVHDLParser#use-cases), he...

> it'd be really nice to eventually have a generic HDL extension in sphinx-contrib that anyone can use with pip and sphinx. Distribution is probably the second most complex challenge...

> Support of markdown and Wavedrom There is a wavedrom extension for Sphinx already. Maybe docstrings can have an optional language keyword, similarly to code blocks in markdown or rst,...

> FYI, someone is advertising the CESNET repo [on Reddit](https://www.reddit.com/r/FPGA/comments/siin1n/sphinxvhdl_automatic_generation_of_documentation/). Maybe it woulw make more sense to start from that project and expand? See https://gitter.im/ghdl1/Lobby?at=61336cb85cfd665e5208f098 > *I just saw that...

> My guess is that the instructions in the neorv32_application_image.vhd were not valid for some reason. Several CPU extensions are disabled by default: https://github.com/stnolting/neorv32/blob/main/rtl/core/neorv32_top.vhd#L59-L71. You might try enabling them all....