core_ftdi_bridge IP for vivado block design

[collins4you]

Hi, I'm trying to wrapping "core_ftdi_bridge" inside a new vivado IP with an axi master to use it directly with my block design. So the question is : have you already a vivado IP done ? Bytheway i'm trying to do it, not so easy to discover what to do with all useless axi4 signals for this wrapping (AN ug1037 ) : m00_axi_init_axi_txn : in std_logic; m00_axi_txn_done : out std_logic; m00_axi_error : out std_logic; m00_axi_awsize : out std_logic_vector(2 downto 0); 8-1024 m00_axi_awlock : out std_logic; nop m00_axi_awcache : out std_logic_vector(3 downto 0);0011 m00_axi_awprot : out std_logic_vector(2 downto 0);000 m00_axi_awqos : out std_logic_vector(3 downto 0);nop m00_axi_awuser : out std_logic_vector(C_M00_AXI_AWUSER_WIDTH-1 downto 0); m00_axi_wuser : out std_logic_vector(C_M00_AXI_WUSER_WIDTH-1 downto 0); m00_axi_buser : in std_logic_vector(C_M00_AXI_BUSER_WIDTH-1 downto 0); m00_axi_arsize : out std_logic_vector(2 downto 0); m00_axi_arlock : out std_logic; m00_axi_arcache : out std_logic_vector(3 downto 0); m00_axi_arprot : out std_logic_vector(2 downto 0); m00_axi_arqos : out std_logic_vector(3 downto 0); m00_axi_aruser : out std_logic_vector(C_M00_AXI_ARUSER_WIDTH-1 downto 0); m00_axi_ruser : in std_logic_vector(C_M00_AXI_RUSER_WIDTH-1 downto 0);

thanks to read me, Colin