ufrisk
how to send tlp than 128bit?
How to encapsulate a write TLP with a 64 bit address that can only send TLP packets with no more than 128 bits at a time.I hope to receive a solution, thank you very much。
The firmware supports this in the most recent firmware versions published in this repo.
PCILeech (LeechCore) does not however utilize this by default and there would have to be code changes in device_fpga.c to accommodate for this.
I don't really have any plans on implementing this in LeechCore though. 128 byte TLPs are guaranteed to always work whilst larger TLPs would be dependent on the system. Also, the performance gain would be negligible.
Thank you very much, I have seen the relevant code.
In some devices, Expansion ROM is used, and I think the system is accessing this area using the tlp of memRead. I don't know if it's correct. Should I handle the corresponding tlp in pcileech_tlps128_mar_controller.sv?
Oh, you mean in the bar controller in the firmware. I'm not sure it supports 256 byte TLPs fully, I'd have to look into that in the coming month or so.
A warning tho, it might be better to complete the 256 byte read in multiple CplD packets consisting of maximum 128 byte each for best compatibility. Not all systems supports 256 byte TLPs (the more recent ones do).
But I should look into this...
What I mean is that Expansion ROM is different from BAR space. like BAR0 is valid, tlps_in.tuser[2] = 1 BAR1 is valid, tlps_in.tuser[3] = 1 BAR2 is valid, tlps_in.tuser[4] = 1 BAR3 is valid, tlps_in.tuser[5] = 1 BAR4 is valid, tlps_in.tuser[6] = 1 BAR5 is valid, tlps_in.tuser[7] = 1 What does tlps_in.tuser [8]=1 represent? Does it represent addresses in other non BAR spaces?
The OPTROM is handled as BAR[6] from the FPGA point of view, so tlps_in.tuser [8]=1 should probably work.