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VCS simulation not working
Impact: software
Tell us about your environment:
Chipyard Version: 1.5.0, Hash: b5d013
OS: centos-release-7-9.2009.1.el7.centos.x86_64
Other: VCS version Q-2020.03-SP1-1
What is the current behavior?
Vsim-based BOOM simulators display the following error when running the built ./simv-chipyard-* executable:
TARGET (RISC-V BINARY) OPTIONS
These are the options passed to the program executing on the emulated RISC-V
microprocessor.
terminate called after throwing an instance of 'std::invalid_argument'
what(): No binary specified (Did you forget it? Did you forget '+permissive-off' if r
Error-[DPI-UED] C++ Exception detected
Import DPI routine invoked at file
'/home/grads/g/georges/fuzz/chipyard/sims/vcs/generated-src/chipyard.TestHarness.Smallline
53) has C++ exceptions not caught. C++ exceptions shall not propagate out of
any imported subroutine.
Fix it in DPI-C code before running simulation.
When running the executable with an -h flag, the following error is displayed at the beginning of the output:
Warning-[RT_UO] Unsupported option
Unsupported option '-h' is ignored
What is the expected behavior? Simulation executables based on vcs run correctly with no errors thrown.
Other information
- The equivalent verilator-based executable works fine
Are you manually invoking the VCS binary? Or using the built in make commands.
Either way this is a bug, since VCS should behave same as Verilator. But using the built in Make commands may sidestep this issue.
I have been using the built in make commands, with flags/arguments that worked for the verilator equivalent.
Le 3 juil. 2021 à 11:28 AM, Jerry Zhao @.***> a écrit :
Are you manually invoking the VCS binary? Or using the built in make commands.
Either way this is a bug, since VCS should behave same as Verilator. But using the built in Make commands may sidestep this issue.
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That is the command to build the simulator. What command are you using to run the simulation.
simv-chipyard-SmallBoomConfig ../../tests/hello.v
It doesn't work when adding executables or additional flags like +verbose, even when configured for verbose output
Sorry. That was a typo on my part. Any riscv binary compiled with https://chipyard.readthedocs.io/en/latest/Software/Baremetal.html gives the same result when combined with +verbose. The simulator works when only given a .riscv file, but doesn't when using any flag, including -h or +verbose.
For example, a command like simv-chipyard-SmallBoomConfig ../../tests/hello.v works, but commands like:
-
simv-chipyard-SmallBoomConfig +verbose ../../tests/hello.v -
simv-chipyard-SmallBoomConfig -hdo not
I think @jerryz123 was talking about execution make commands such as make run-binary and make run-binary-hex.
If you are invoking the simulator directly and trying to add VCS flags, you might want to add the +permissive and +permissive-off flags before an after you VCS plug args.
Hello, I am facing the same error with vcs when trying the vlsi flow as I want to simulate my design. I use the command "make sim-rtl CONFIG=TinyRocketConfig BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv32ui-p-simple" as in the ASAP7 example . Can you help me if you figured out anything ?
