Tynan McAuley
Tynan McAuley
Turns out the interaction between the various AXI widgets and the TLFIFOFixer is pretty subtle, so I'm going to move that discussion to this thread in the Chipyard Google Group:...
Added this PR for experimenting with the fix: https://github.com/ucb-bar/barstools/pull/120
No problem, thanks for the confirmation! Let me know if I can do anything to help out. I can certainly submit a PR to fix these logical bugs in the...
Hey @mikeurbach, is there any update on this issue? I'd love to get https://github.com/llvm/circt/pull/6719 re-merged if possible.
> I don't think anyone has been looking at addressing this. I could reproduce the issue on an internal design, but I never got around to writing a small FIRRTL...
https://github.com/ucb-bar/chipyard/pull/2207 contains the changes to remove uses of `ChiselAnnotation` outside of firesim.
Status update: https://github.com/ucb-bar/fixedpoint/pull/11 is working, but I'm going to leave it in a draft state until Chisel 7 is released (it's currently pointing to a recent SNAPSHOT release).
> what about feedback from a register/memory to its clock input(s)? seems similar enough... While it might not be the most common use-case for FIRRTL users, a feedback path from...
Ha, I just ran into this same error and was about to file an issue for it, before I saw this one :P
Okay, I came up with a _way_ simpler reproduction. The issue seems to originate from indexing into a FIRRTL aggregate from a layer, when aggregate preservation is enabled. ```scala //>...