Thorsten Schütt

There are SVE registers. The calling convention can probably pass scalable vectors on the stack. Then it will be vscale * 1 bytes. It has to be a *fixed* size.

If you have too much time, you can actually play with a SVE box: https://github.com/aws/aws-graviton-getting-started The other option is a Fujitsu box. It is a harder problem to get access.

One selling point of SVE is: if you use ARM ACLE SVE intrinsics and you follow the rules, then your program will run on 256-bit and 2048-bit hardware. ARM SVE...

```shell > wc -l arm_sve.h 24043 arm_sve.h ```

Sorry for my misbehaviour. I am supportive of adding scalable vectors to Rust. Because of type inference you cannot see that the `pred` variable is a predicate.

The real questions is whether you want to make scalable vectors target-dependent (SVE, RISC-V). I still like this `f64xN`. Scalable vectors of `f64`. rustc or LLVM can make it target-dependent:...

Note that vscale is a LLVM thing and should not be part of the RFC. LLVM assumes the vscale is an unknown but constant value during the execution of the...

Do you want to expose this in Rust or should it be a an implementation detail of the compiler?

How about this notation (without the 4): ```rust #[repr(simd, scalable)] #[derive(Clone, Copy)] pub struct svfloat32_t { _ty: [f32; 0], } ``` It is a target-indent scalable vector of `f32`. If...

Honestly my RISC-V knowledge is limited. If you say that `MUL` is 4, then you make it target-dependent. It most likely only works for SVE. If In the future there...