uarch-bench
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travisdowns
A benchmark for low-level CPU micro-architectural features
The current solution in `uarch-bench.sh` to disable turbo mode (write to msr regs) only works for Intel, but we should come up with a solution for AMD. I didn't find...
You note the effect for Skylake on the wiki ("Minimum store-forwarding latency is 3 on new(ish) chips, but the load has to arrive at exactly the right time to achieve...
Many users will probably just `git clone` followed by `make` and the submodules will be missing in that case, but the failure mode is a bit obscure: you'll get some...
Currently, each `TIMER` implementation should implement a static `now()` method, which is used in the core of the benchmark loop in order to take time (or PMU or whatever other...
*uarch-bench.sh* contains multiple calls to `sudo`, which obviously won't work if the system doesn't have `sudo` installed (Debian minimal doesn't come installed with sudo). You could test to see if...
Currently we are only getting user-mode cycles from libpfc. We should probably track all cycles.
I really like your tool, Travis! And it would be even more cool to have web version like https://gcc.godbolt.org/ or http://quick-bench.com/ The use case that I'm looking for is that...
Right now we just hardcode some column sizes, an annoying tradeoff in many cases. Let's property pretty-print our tables with dynamic column sizing.
If you run `./uarch-bench.sh` on AMD, it will fail when it tries to write to the turbo-disabling MSRs which are Intel-specific. We should skip this step on AMD.
Currently we just measure the absolute time of the code under test like so: static int64_t time_method(size_t loop_count) { auto t0 = CLOCK::now(); METHOD(loop_count); auto t1 = CLOCK::now(); return t1...
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A benchmark for low-level CPU micro-architectural features