Travis Downs
Travis Downs
The current solution in `uarch-bench.sh` to disable turbo mode (write to msr regs) only works for Intel, but we should come up with a solution for AMD. I didn't find...
Many users will probably just `git clone` followed by `make` and the submodules will be missing in that case, but the failure mode is a bit obscure: you'll get some...
Currently, each `TIMER` implementation should implement a static `now()` method, which is used in the core of the benchmark loop in order to take time (or PMU or whatever other...
Currently we are only getting user-mode cycles from libpfc. We should probably track all cycles.
Right now we just hardcode some column sizes, an annoying tradeoff in many cases. Let's property pretty-print our tables with dynamic column sizing.
If you run `./uarch-bench.sh` on AMD, it will fail when it tries to write to the turbo-disabling MSRs which are Intel-specific. We should skip this step on AMD.
Currently we just measure the absolute time of the code under test like so: static int64_t time_method(size_t loop_count) { auto t0 = CLOCK::now(); METHOD(loop_count); auto t1 = CLOCK::now(); return t1...
Currently every file that defines benchmarks needs to declare a benchmark registration method that is called explicitly in `make_benches` in `main.cpp` which look like: ``` template GroupList make_benches() { GroupList...
Rather than compiling in benchmarks, it would be cool to allow benchmarks to be dynamically loaded from a shared object, allowing decoupling of the benchmark application and default benchmarks from...
If you include on the command line: --timer=libpfc --extra-events=FRONTEND_RETIRED.L1I_MISS You'll see this output: ``` Event 'FRONTEND_RETIRED.L1I_MISS' resolved to 'skl::FRONTEND_RETIRED:L1I_MISS:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0:fe_thres=0, short name: 'FRONTE' with code 0x5301c6 Event 'FRONTEND_RETIRED.L1I_MISS' resolved to 'skl::FRONTEND_RETIRED:L1I_MISS:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0:fe_thres=0,...