rising drck edge very close before csn goes low

[inkdot7]

Hi!

This is just something I noticed, which I am not sure if it is a potential problem, or actually intended.

(Background: I had problems to read data from SPI flash on a Digilent Arty A7 board from within the FPGA, so eventually resorted to hack the spiOverJtag to see working signals on a scope and compare to my issue. Turned out I had swapped sdo and sdi...)

The picture below is from spiOverJtag doing a read command (0x03), where the transfer of the 00000011 bits of 0x03 is marked with yellow and blue for the six 0 and two 1 command bits. What I am a bit worried about is the drck rising edge very close before the chip select csn going low (at the red paint mark).

openFPGAloader is working very well for me, so I do not know if this is something to worry about. The drck transition is ~1.5 ns before the csn transition, so quite close in terms of cable lengths and unexpected propagation delays. If it would be seen by the flash chip after csn going low, it could sample the first command bit there?