Tianqi Chen comments

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                                            Tianqi Chen

[SVE] Change the dtype of Ramp and Broadcast lanes to PrimExpr

if it is not high effort, consider add https://github.com/apache/tvm/blob/main/python/tvm/ir/json_compact.py so previously serialized node can be loaded

[Target] Use LLVM target parser for determining Arm(R) A-Profile Architecture features

I am also getting additional errors like ``` python test.py [15:23:28] /home/tqchen/github/tvm/src/target/parsers/aprofile.cc:97: Warning: Cannot parse target features. LLVM was not compiled with support for Arm(R)-based targets. [15:23:28] /home/tqchen/github/tvm/src/target/parsers/aprofile.cc:97: Warning: Cannot...

[Relax][Runtime] RNNState for Space State Models

please fix the lint error

[VM] [Hexagon] Introduce 2D Discontiguous vtcm alloc tensor

sorry for getting into this late. I see we introduced some metadata by having a map from pointer to metadata, @quic-sanirudh , an alternative would be to introduce a HexagonBuffer...

[VM] [Hexagon] Introduce 2D Discontiguous vtcm alloc tensor

Thanks @quic-sanirudh . I did another round provided all the feedbacks, let me know if they make sense

[VM] [Hexagon] Introduce 2D Discontiguous vtcm alloc tensor

happy to get it in @quic-sanirudh to unblock folks, let us followup and try remove the phyiscal map by embedding them in buffer descriptor

[VM] [Hexagon] Introduce 2D Discontiguous vtcm alloc tensor

@tvm-bot rerun

[Unity][Parser] Check well-formedness in the parser

Unfortunately we find that the pr caused an outage of the MLC compilation, seems to relates to `MergeSharedMemoryAllocations` location change. We should also carve out a UT from failed TIR...

[TIR][CUDA] Add native FP8 support to codegen

please checkin on the ci issues, likely we need requires_cuda tag?

[TIR][CUDA] Add native FP8 support to codegen

@tvm-bot rerun