Thomas Watson

New IR causes DSP inference issues with Quartus

1

The following design (within the Details) infers 2 DSP blocks: `Info (21062): Implemented 2 DSP elements`. ```python from amaranth import * from amaranth.lib import wiring from amaranth.lib.wiring import In, Out...

#### Code Sample, a copy-pastable example if possible ```python from pyproj import CRS, Transformer from pyproj.aoi import AreaOfInterest from pyproj.database import query_utm_crs_info def broken(lat, lon): aoi = AreaOfInterest( west_lon_degree=lon, south_lat_degree=lat,...

Implement batch transmission and better testing features

7

Requires [modification](https://github.com/ODM2/ODM2DataSharingPortal/issues/649) to the MonitorMyWatershed site to work properly. This PR has been marked as a draft until those changes are made. This implementation of the protocol reuses the logic...

It does not show data and instead shows ` TypeError: a[0].RXa is undefined `. Templating gone wrong?

Not sure when exactly it happened, but at some point the logs switched from `MAG`, `MAG2`, etc. to `MAG.I==0`, `MAG.I==1`, etc. For these newer logs data from all the magnetometers...

Zero-length submodule name breaks things

4

The following design: ``` from amaranth import * from amaranth.back import verilog class Bar(Elaboratable): def elaborate(self, platform): m = Module() m.d.sync += Signal().eq(1) return m class Foo(Elaboratable): def elaborate(self, platform):...

Enforce naming rules on core HDL

2

The rules are quite simple and liberal: * Can't be None or the empty string (case-specific exceptions) * Can't contain a Unicode separator character * Can't contain a Unicode control...

I was wondering if you had a derivation for the licensing server too necessary to use vGPU functionality.

Please see commits for details.

How to manage memory?

4

I have a simple script which loads a bunch of files using `pycc.FileIOFilter.LoadFromFile`, but I cannot figure out how to destroy the `ccHObject`s that it returns. Thus, the loaded files...