high-level-synthesis topic
heterocl
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
cho
CHO is a benchmark suite for OpenCL FPGA Accelerators
HLS-CNN
High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
High-Level-Synthesis
Convert C files into Verilog
CHARM
CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture
hcl-dialect
HeteroCL-MLIR dialect for accelerator design
metalfs
Near-storage compute aware file system and FPGA operator pipelines.
hls_tutorials
Tutorials on HLS Design
NoCpad
HLS for Networks-on-Chip
FADO
[FPGA 2023] FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs