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This adds several improvements to the converters from and to fixed point: - Fixed point to floating point now supports fractional bits - Uses AFix and Flow in I/O -...

fayalalebrun

Maybe a little more optimal for an FPGA...

1

"(delta_part_a + delta_part_b)" can be "(delta_part_a } delta_part_b)", replacing an adder with an OR operation, which might be slightly quicker or use less resource if implemented in H/W.

hamsternz

More marketable name?

2

With #8, I think the library will become interesting for a wider audience, now also including VHDL and Verilog users. However, at the moment the name of the library is...

fayalalebrun