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          YARI -- Yet Another RISC Implementation

Last update: 2010-09-04

INTRODUCTION

YARI is an high performance soft core RISC implementation, binary compatible with a subset of MIPS R3000.

This README will be out of date at the time you read this, but the implementation currently comprises:

• A reference simulator which closely matches the RTL implementation (in fact they co-simulate).

• A few regression and tests programs

• An RTL (Verilog) implementation

  Core features:

  • an eight stage pipeline.
  • a 4-way associative write-through instruction cache (default 8 KiB)
  • a 4-way associative write-through data cache (default 16 KiB)
  • a store buffer
  • all of the integer user-level instructions supported

  Peripherals (depending on the target)

  • Async SRAM interface (32-bit and 16-bit)
  • Sync burst SRAM interface (32-bit)
  • Serial in/out
  • 1024x768x8 video interface

  Simulation

  • Enough support to fully simulate the RTL with Icarus Verilog.
  • Co-simulation against the reference simulator supported

  Synthesis

  • Multiple target platforms supported (currently only Altera based)
  • Runs at 80+ MHz.

• A boot loader pre-loaded into the I$ - will load programs over the serial port.

• Assorted tools to turn the elf binaries into ROM and RAM images.

GETTING STARTED

There are a few prerequisites for full YARI enjoyment:

• For building any test programs: Cross compilation tool much be built (mips-elf-gcc, etc). The script xtools/BUILD is what I used to build them

• For simulation: Icarus Verilog. Great stuff. Get the most recent version from http://www.icarus.com/eda/verilog

• For synthesis: currently I've only tested with Quartus 7.2sp1, 8.0, 8.0sp1, and 10.0. Get it for free from http://www.altera.com.

With the Icarus Verilog installed you should be able to simply run

make rtlsim

and see the trace of instructions as the Verilog implementation makes it through a small self-checking regression test.

For more interesting workloads, try

make -C testcases VERB= PROG=buzzard isasim

or try co-simulation

make -C testcases VERB= PROG=fib cosim