Tom Clarke
Tom Clarke
There are some special cases where auto-route should be better - When connecting opposite edges of a component, the wire should go *round* the component, not through it - 3...
The following components would be useful on Issie: * Signed and unsigned bus extend * Currently there is no way to do this except an ugly one with multiplexor and...
This is motivated by #442 Currently, whenever SVG radix or zoom is changed, waveform SVGs are recreated. We recreate (typically) 1000 cycles of the SVG even if we are only...
Issie uses a lot of numeric SVG text display in the waveform simulator - some of which is time-critical. This is challenging because: * Numeric values can be anything from...
**Describe the bug** White-screen crash with issie unresponsive after has been reported when doing long simulations of large designs. **To Reproduce** Not yet enough information **Additional context** This was reported...
**Is your feature request related to a problem? Please describe.** Curently, after simulating a very long simulation, moving backwards to examine the history beyond the 1000 clock cycle buffer requires...
This issue has three parts, which need not all be done together. 1. Speed up waveform SVG generation by generating only the displayed part of the waveforms (normally approx 1/40...
**Is your feature request related to a problem? Please describe.** Currently simulations cannot continue for more than approx 2,000,000,000 clock cycles (2^31 - 1) because time is represented by an...
Currently the Issie wire separation does not always make same-net wires that can overlap each other from their source port do this. this makes it burdensome to route long connections...