issie
issie copied to clipboard
tomcl
Issie - an intuitive cross-platform hardware design application. https://tomcl.github.io/issie
**Is your feature request related to a problem? Please describe.** "Differentiate consecutive blocks with distinct colors in the wave simulation, making it easier to interpret the simulated results. Additionally, for...
**Is your feature request related to a problem? Please describe.** "When using the merge wire component, it would be helpful if the software automatically identifies the input that connects to...
**Describe the bug** Waveform selection is not persistent across project open/close **To Reproduce** There is also a small bug in the wave simulation. It appears that after changing the wave...
**Describe the bug** Combinational Verilog components which are edited can be cancelled without saving. This loses all the edits - there should be a confirmation dialog in this case. **To...
## Demo [See a demo on my branch here.](https://timothycdc.github.io/issie/) ## Info Previously, the repo relied on Jekyll to build a blog that provides a general description of Issie and the...
## Overview Add functionality to set 'groups of symbols', used for HLP25. Also adds a deterministic colour generator for groups, using poisson-disk sampling for distantly-spaced colours that do not clash...
## General Summary of changes (non-exhaustive) ### CommonTypes - Rectangle Type added for easier calculation ### BlockHelpers - Extended intersection helpers to all cases (1d, 2d, 1d with 2d) -...
Features: - Shows mouse position and the id of hovered component/wire. - Select a symbol to view its component info, ports, and port maps. - Select a wire to view...
**Describe the bug** Issie pre-5.1.0 had a memory leak that caused slowdown and then crashing after long use. The leakage scales with edited sheet size so when editing a large...
Content pending review of codebase and discussion with Dr. Clarke.
