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tomcl
Issie - an intuitive cross-platform hardware design application. https://tomcl.github.io/issie
Currently the initialisation of RAM/ROM is only configurable when creating a new one. It'd be better if it's changeable later in properties so that we don't need to create a...
**Issue by [tomcl](https://github.com/tomcl)** _Friday Jun 19, 2020 at 20:43 GMT_ _Originally opened as https://github.com/MarcoSelvatici/DEflow/issues/53_ ---- Asynchronous logic is not suitable for 1st year students. However there is one common case...
This is motivated by #442 Currently, whenever SVG radix or zoom is changed, waveform SVGs are recreated. We recreate (typically) 1000 cycles of the SVG even if we are only...
Issie uses a lot of numeric SVG text display in the waveform simulator - some of which is time-critical. This is challenging because: * Numeric values can be anything from...
**Describe the bug** White-screen crash with issie unresponsive after has been reported when doing long simulations of large designs. **To Reproduce** Not yet enough information **Additional context** This was reported...
**Is your feature request related to a problem? Please describe.** Curently, after simulating a very long simulation, moving backwards to examine the history beyond the 1000 clock cycle buffer requires...
This issue has three parts, which need not all be done together. 1. Speed up waveform SVG generation by generating only the displayed part of the waveforms (normally approx 1/40...
**Is your feature request related to a problem? Please describe.** Currently simulations cannot continue for more than approx 2,000,000,000 clock cycles (2^31 - 1) because time is represented by an...
Currently the Issie wire separation does not always make same-net wires that can overlap each other from their source port do this. this makes it burdensome to route long connections...